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1. general description the PCA2125 is a cmos real-time clock/calendar optimized for low-power consumption and an operating temperature up to 125 c. data is transferred via a serial peripheral interface (spi) bus with a maximum data rate of 6.0 mbit/s. an alarm and timer function are also available with the possibility to generate a wake-up signal on an interrupt pin. aec q100 quali?ed for automotive applications. 2. features n provides year, month, day, weekday, hours, minutes and seconds based on 32.768 khz quartz crystal n resolution: seconds to years n clock operating voltage: 1.3 v to 5.5 v n low backup current: typical 0.55 m a at v dd = 3.0 v and t amb = 25 c n 3-line spi-bus with separate combinable data input and output n serial interface (at v dd = 1.6 v to 5.5 v) n 1 second or 1 minute interrupt output n freely programmable timer with interrupt capability n freely programmable alarm function with interrupt capability n integrated oscillator capacitor n internal power-on reset n open-drain interrupt pin 3. applications n automotive time keeping application n metering 4. ordering information PCA2125 spi real-time clock/calendar rev. 01 28 july 2008 product data sheet table 1. ordering information type number package name description version PCA2125ts tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 2 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar 5. marking 6. block diagram table 2. marking codes type number marking code PCA2125ts PCA2125 fig 1. block diagram of PCA2125 001aah664 PCA2125 oscillator 32.768 khz divider clock out interrupt clkout int monitor power-on reset watch- dog spi interface osci ce scl sdi sdo osco v dd v ss timer function timer_control 0eh countdown_timer 0fh control control_1 00h control_2 01h clkout_control 0dh time seconds 02h minutes 03h hours 04h days 05h alarm function minute_alarm 09h hour_alarm 0ah day_alarm 0bh weekday_alarm 0ch weekdays 06h months 07h years 08h
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 3 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar 7. pinning information 7.1 pinning 7.2 pin description 8. functional description the PCA2125 contains sixteen 8-bit registers with an auto-incrementing address register, an on-chip 32.768 khz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the real-time clock (rtc), a programmable clock output, and a 6 mhz spi-bus. all sixteen registers are designed as addressable 8-bit parallel registers although not all bits are implemented: fig 2. pin con?guration for tssop14 PCA2125 osci v dd osco clkout n.c. n.c. n.c. n.c. int scl ce sdi v ss sdo 001aaf892 1 2 3 4 5 6 7 8 10 9 12 11 14 13 table 3. pin description symbol pin description osci 1 oscillator input osco 2 oscillator output n.c. 3, 4 not connected; do not connect and do not use as feed through; connect to v dd if ?oating pins are not allowed int 5 interrupt output (open-drain; active low) ce 6 chip enable input (active high) with 200 k w pull-down resistor v ss 7 ground sdo 8 serial data output, push-pull sdi 9 serial data input; might ?oat when ce inactive scl 10 serial clock input; might ?oat when ce inactive n.c. 11, 12 not connected; do not connect and do not use as feed through; connect to v dd if ?oating pins are not allowed clkout 13 clock output (open-drain) v dd 14 supply voltage
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 4 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar ? the ?rst two registers at addresses 00h and 01h (control_1 and control_2) are used as control registers. ? registers at addresses 02h to 08h (seconds, minutes, hours, days, weekdays, months, years) are used as counters for the clock function. seconds, minutes, hours, days, months and years are all coded in binary coded decimal (bcd) format. when one of the rtc registers is read the contents of all counters are frozen. therefore, faulty reading of the clock/calendar during a carry condition is prevented. ? registers at addresses 09h to 0ch (minute_alarm, hour_alarm, day_alarm, weekday_alarm) de?ne the alarm condition. ? register at address 0dh (clkout_control) de?nes the clock out mode. ? registers at addresses 0eh and 0fh (timer_control and countdown_timer) are used for the countdown timer function. the countdown timer has four selectable source clocks allowing for countdown periods in the range from less than 1 ms to more than 4 hours. there are also two pre-de?ned timers which can be used to generate an interrupt once per second or once per minute. these are de?ned in register control_2 (01h). 8.1 register overview the time registers are encoded in bcd to simplify application use. other registers are either bit-wise or standard binary. [1] tens place. table 4. register overview bits labeled - are not implemented and will return a logic 0 when read. bit positions labeled 0 should always be written with logic 0. address register name bit 7 6 5 4 3 2 1 0 00h control_1 ext_test 0 stop 0 por_ovrd 12_24 0 0 01h control_2 mi si msf ti_tp af tf aie tie 02h seconds rf seconds [1] seconds 03h minutes - minutes [1] minutes 04h hours - - ampm hours [1] hours - - hours [2] hours 05h days - - days [1] days 06h weekdays - - - - - weekdays 07h months - - - months [1] months 08h years years [1] years 09h minute_alarm aen_m minute_alarm [1] minute_alarm 0ah hour_alarm aen_h - ampm hour_alarm [1] hour_alarm - hour_alarm [2] hour_alarm 0bh day_alarm aen_d - day_alarm [1] day_alarm 0ch weekday_alarm aen_w - - - - weekday_alarm 0dh clkout_control - - - - - cof 0eh timer_control te - - - - - ctd 0fh countdown_timer countdown_timer
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 5 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar [2] tens place in 24 h mode. 8.2 reset the PCA2125 includes an internal reset circuit which is active whenever the oscillator is stopped; see figure 3 . the oscillator can be stopped, for example, by connecting one of the oscillator pins osci or osco to ground. the oscillator is considered to be stopped during the time between power-up and stable crystal resonance; see figure 4 . this time can be in the range 200 ms to 2 s depending on crystal type, temperature and supply voltage. whenever an internal reset occurs, the reset ?ag bit rf is set. fig 3. reset system fig 4. power-on reset table 5. register reset value bits labeled - are not implemented and will return a 0 when read. bits labeled x are unde?ned at power-up and unchanged by subsequent resets. address register name bit 7 6 5 4 3 2 1 0 00h control_1 0 0 0 - 1 0 - - 01h control_2 00000000 02h seconds 1 xxxxxxx 03h minutes - xxxxxxx 04h hours - - xxxxxx 05h days - - xxxxxx 06h weekdays -----xxx 001aaf898 sdi ce 0 = override inactive 0 = clear override mode 0 = stopped, 1 = running osc stopped 1 = override active 1 = override possible clear por override bit por_ovrd oscillator reset 001aaf897 chip in reset chip not in reset t v dd oscillation internal reset
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 6 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar after reset, the following mode is entered: ? 32.768 khz on pin clkout active ? power-on reset override available to be set ? 24 hour mode is selected the spi-bus is initialized whenever the chip enable pin ce is inactive (low). 8.2.1 power-on reset override the power-on reset (por) duration is directly related to the crystal oscillator start-up time. due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the por and hence speed up the on-board test of the device. the setting of this mode requires that bit por_ovrd be set to logic 1 and that the signals at the spi-bus pins sdi and ce are toggled as illustrated in figure 5 . all timings are required minimums. once the override mode has been entered, the device immediately stops being reset and set-up operation can commence i.e. entry into the external clock test mode via the spi-bus access. the override mode can be cleared by writing a logic 0 to bit por_ovrd. bit por_ovrd must be set to logic 1 before a re-entry into the override mode is possible. setting bit por_ovrd to logic 0 during normal operation has no effect except to prevent accidental entry into the por override mode. this is the recommended setting. 07h months - - - xxxxx 08h years xxxxxxxx 09h minute_alarm 1 xxxxxxx 0ah hour_alarm 1 - xxxxxx 0bh day_alarm 1 - xxxxxx 0ch weekday_alarm 1 ----xxx 0dh clkout_control -----000 0eh timer_control 0 -----11 0fh countdown_timer xxxxxxxx table 5. register reset value continued bits labeled - are not implemented and will return a 0 when read. bits labeled x are unde?ned at power-up and unchanged by subsequent resets. address register name bit 7 6 5 4 3 2 1 0 fig 5. por override sequence 001aaf900 minimum 500 ns minimum 2000 ns por override set at this time sdi ce reset override minimum 500 ns
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 7 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar 8.3 control registers table 6. control_1 register (address 00h) bit description bit symbol value description reference 7 ext_test 0 normal mode section 8.9 1 external clock test mode 6 - 0 unused 5 stop 0 rtc source clock runs section 8.10 1 rtc divider chain ?ip-?ops are asynchronously set to logic 0; the rtc clock is stopped (clkout at 32.768 khz, 16.384 khz or 8.192 khz is still available) 4 - 0 unused - 3 por_ovrd 0 power-on reset override facility is disabled; set to logic 0 for normal operation section 8.2.1 1 power-on reset override is enabled 2 12_24 0 24 hour mode is selected t ab le 11 1 12 hour mode is selected 1 to 0 - 0 unused - table 7. control_2 register (address 01h) bit description bit symbol value description reference 7 mi 0 minute interrupt is disabled section 8.6.1 1 minute interrupt is enabled 6 si 0 second interrupt is disabled 1 second interrupt is enabled 5 msf 0 no minute or second interrupt generated section 8.6 1 ?ag set when minute or second interrupt generated; ?ag must be cleared to clear interrupt 4 ti_tp 0 interrupt pin follows timer ?ags section 8.7.2 1 interrupt pin generates a pulse 3 af 0 no alarm interrupt generated section 8.5.1 1 ?ag set when alarm triggered; ?ag must be cleared to clear interrupt 2 tf 0 no countdown timer interrupt generated - 1 ?ag set when countdown timer interrupt generated; ?ag must be cleared to clear interrupt - 1 aie 0 no interrupt generated from the alarm ?ag section 8.7.3 1 interrupt generated when alarm ?ag set 0 tie 0 no interrupt generated from the countdown timer ?ag section 8.7 1 interrupt generated when countdown timer ?ag set
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 8 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar 8.4 time and date function the majority of the registers are coded in the binary coded decimal (bcd) format. bcd is used to simplify application use. an example is shown for register minutes in t ab le 8 . [1] hour mode is set by bit 12_24 in register control_1. table 8. bcd example minutes value (decimal) double-digit digit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2 3 2 2 2 1 2 0 2 3 2 2 2 1 2 0 00 00000000 01 00000001 02 00000010 : :::::::: 09 00001001 10 00010000 : :::::::: 58 01011000 59 01011001 table 9. register seconds (address 02h) bit description bit symbol value description 7 rf 0 clock integrity is guaranteed 1 clock integrity is not guaranteed; chip reset has occurred since ?ag was last cleared 6 to 0 seconds[6:0] 00 to 59 this register holds the current seconds value coded in bcd format table 10. register minutes (address 03h) bit description bit symbol value description 7 - 0 unused 6 to 0 minutes[6:0] 00 to 59 this register holds the current minutes value coded in bcd format table 11. register hours (address 04h) bit description bit symbol value description 6 and 7 - 0 unused 12 hour mode [1] 5 ampm 0 indicates am 1 indicates pm 4 to 0 hours[4:0] 01 to 12 this register holds the current hours value coded in bcd format for 12 hour mode 24 hour mode [1] 5 to 0 hours[5:0] 00 to 23 this register holds the current hours value coded in bcd format for 24 hour mode
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 9 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar [1] the rtc compensates for leap years by adding a 29th day to february if the year counter contains a value which is exactly divisible by 4, including the year 00. [1] the weekday assignments can be re-de?ned by the user. table 12. register days (address 05h) bit description bit symbol value description 6, 7 - 0 unused 5 to 0 days[5:0] 01 to 31 this register holds the current day value coded in bcd format [1] table 13. register weekdays (address 06h) bit description bit symbol value description 3 to 7 - 0 unused 2 to 0 weekdays[2:0] 0 to 6 this register holds the current weekday value; see t ab le 14 table 14. weekday assignments day [1] double-digit digit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sunday x xxxx0 0 0 monday x xxxx0 0 1 tuesday x xxxx0 1 0 wednesday x xxxx0 1 1 thursday x xxxx1 0 0 friday xxxxx1 0 1 saturday x xxxx1 1 0 table 15. register months (address 07h) bit description bit symbol value description 5 to 7 - 0 unused 4 to 0 months[4:0] 01 to 12 this register holds the current month value coded in bcd format; see t ab le 16 table 16. month assignments month double-digit digit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 january xxx00001 february x x x 0 0 0 1 0 march x x x 0 0 0 1 1 april x x x 0 0 1 0 0 may xxx00101 june x x x 0 0 1 1 0 july x x x 0 0 1 1 1 august x x x 0 1 0 0 0 september x x x 0 1 0 0 1
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 10 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar figure 6 shows the data ?ow and data dependencies starting from the 1 hz clock tick. 8.5 alarm function when one or several alarm registers are loaded with a valid minute, hour, day or weekday value and its corresponding alarm enable not bit (aenx) is logic 0, then that information is compared with the current minute, hour, day and weekday value. october x x x 1 0 0 0 0 november x x x 1 0 0 0 1 december x x x 1 0 0 1 0 table 17. register years (address 08h) bit description bit symbol value description 7 to 0 years[7:0] 00 to 99 this register holds the current year value coded in bcd format fig 6. data ?ow for the time function table 16. month assignments continued month double-digit digit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 001aaf901 1 hz tick 12_24 hour mode weekday seconds minutes hours days leap year calculation months years table 18. register minute_alarm (address 09h) bit description bit symbol value description 7 aen_m 0 minute alarm is enabled 1 minute alarm is disabled 6 to 0 minute_alarm[6:0] 00 to 59 this register holds the minute alarm value coded in bcd format
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 11 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar table 19. register hour_alarm (address 0ah) bit description bit symbol value description 7 aen_h 0 hour alarm is enabled 1 hour alarm is disabled 6 - 0 unused 12 hour mode 5 ampm 0 indicates am 1 indicates pm 4 to 0 hour_alarm 01 to 12 this register holds the hour alarm value coded in bcd format when in 12 hour mode 24 hour mode 5 to 0 hour_alarm 00 to 23 this register holds the hour alarm value coded in bcd format when in 24 hour mode table 20. register day_alarm (address 0bh) bit description bit symbol value description 7 aen_d 0 day alarm is enabled 1 day alarm is disabled 6 - 0 unused 5 to 0 day_alarm 01 to 31 this register holds the day alarm value coded in bcd format table 21. register weekday_alarm (address 0ch) bit description bit symbol value description 7 aen_w 0 weekday alarm is enabled 1 weekday alarm is disabled 3 to 6 - 0 unused 2 to 0 weekday_alarm 0 to 6 this register holds the weekday alarm value
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 12 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar generation of interrupts from the alarm function is described in section 8.7.3 . 8.5.1 alarm ?ag when all enabled comparisons ?rst match, the alarm ?ag bit af is set. bit af will remain set until cleared by software. once bit af has been cleared it will only be set again when the time increments once more to match the alarm condition. alarm registers which have their bit aenx at logic 1 are ignored. figure 8 shows an example for clearing bit af, but leaving bit msf and bit tf unaffected. the ?ags are cleared by a write command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. repeatedly re-writing these bits has no in?uence on the functional behavior. fig 7. alarm function block diagram 001aaf902 weekday alarm weekday aen weekday time = day alarm day aen day time = hour alarm hour aen hour time = minute alarm minute aen minute time = check now signal set alarm flag, af minute aen = 1 1 0 example example where only the minute alarm is used and no other interrupts are enabled. fig 8. alarm ?ag timing 001aaf903 44 45 45 minute alarm minutes counter af int when aie = 1 46
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 13 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar to prevent the timer ?ags being overwritten while clearing bit af, a logic and is performed during a write access. the ?ag is reset by writing a logic 0 but its value is not affected by writing a logic 1. t ab le 23 shows what instruction must be sent to clear bit af. in this example, bit msf and bit tf are unaffected. 8.6 timer functions the countdown timer has four selectable source clocks allowing for countdown periods in the range from less than 1 ms to more than 4 hours. there are also two pre-de?ned timers which can be used to generate an interrupt once per second or once per minute. registers control_2 (01h), timer_control (0eh) and countdown_timer (0fh) are used to control the timer function and output. 8.6.1 second and minute interrupt the second and minute interrupts (bits si and mi) are pre-de?ned timers for generating periodic interrupts. the timers can be enabled independently of one another, however a minute interrupt enabled on top of a second interrupt will not be distinguishable since it will occur at the same time; see figure 9 . table 22. flag location in register control_2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 control_2 - - msf - af tf - - table 23. example to clear only af (bit 3) in register control_2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 control_2 - - 1 - 0 1 - - table 24. register timer_control (address 0eh) bit description bit symbol value description reference 7 te 0 countdown timer is disabled section 8.6.2 1 countdown timer is enabled 6 to 2 - 0 unused 1 to 0 ctd[1:0] 00 4096 hz countdown timer source clock 01 64 hz countdown timer source clock 10 1 hz countdown timer source clock 11 1 60 hz countdown timer source clock table 25. register countdown_timer (address 0fh) bit description bit symbol value description reference 7 to 0 countdown_timer[7:0] 00h to ffh countdown value = n. section 8.6.2 countdownperiod n sourceclockfrequency -------------------------------------------------------------- - =
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 14 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar the minute and second ?ag (bit msf) is set to logic 1 when either the seconds or the minutes counter increments according to the currently enabled interrupt. the ?ag can be read and cleared by the interface. the status of bit msf does not affect the int pulse generation. if the msf ?ag is not cleared prior to the next coming interrupt period, an int pulse will still be generated. the purpose of the ?ag is to allow the controlling system to interrogate the PCA2125 and identify the source of the interrupt such as the minute/second or countdown timer. a. int and msf when si enabled (msf ?ag not cleared after an interrupt) b. int and msf when only mi enabled bit ti_tp is set to logic 1 resulting in 1 64 hz wide interrupt pulse. fig 9. int example for bits si and mi table 26. effect of bits mi and si on int generation minute interrupt (bit mi) second interrupt (bit si) result 0 0 no interrupt generated 1 0 an interrupt once per minute 0 1 an interrupt once per second 1 1 an interrupt once per second 001aai520 seconds counter minutes counter int msf 58 59 00 59 00 11 12 01 001aai521 seconds counter minutes counter int msf 58 59 00 59 00 11 12 01
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 15 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar [1] in the case of bit mi = 1 and bit si = 0, bit msf will be cleared automatically after 1 second. 8.6.2 countdown timer function the 8-bit countdown timer at address 0fh is controlled by the timer control register at address 0eh. the timer control register determines one of 4 source clock frequencies for the timer (4096 hz, 64 hz, 1 hz, or 1 60 hz), and enables or disables the timer. [1] when not in use, bits ctd[1:0] must be set to 1 60 hz for power saving. remark: note that all timings which are generated from the 32.768 khz oscillator are based on the assumption that there is 0 ppm deviation. deviation in oscillator frequency will result in a corresponding deviation in timings. this is not applicable to interface timing. the timer counts down from a software-loaded 8-bit binary value n. loading the counter with 0 effectively stops the timer. values from 1 to 255 are valid. when the counter reaches 1, the countdown timer ?ag (bit tf) will be set and the counter automatically re-loads and starts the next timer period. reading the timer will return the current value of the countdown counter; see figure 10 . table 27. effect of bits mi and si on bit msf minute interrupt (bit mi) second interrupt (bit si) result 0 0 msf never set 1 0 msf set when minutes counter increments [1] 0 1 msf set when seconds counter increments 1 1 msf set when seconds counter increments table 28. bits ctd1 and ctd0 for timer frequency selection and countdown timer durations bits ctd[1:0] timer source clock frequency delay minimum timer duration n= 1 maximum timer duration n = 255 00 4096 hz 244 m s 62.256 ms 01 64 hz 15.625 ms 3.984 s 10 1 hz 1 s 255 s 11 1 60 hz 60 s [1] 4 h 15 min
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 16 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar if a new value of n is written before the end of the current timer period, then this value will take immediate effect. nxp semiconductors does not recommend changing n without ?rst disabling the counter (by setting bit te = 0). the update of n is asynchronous with the timer clock, therefore changing it without setting bit te = 0 will result in a corrupted value loaded into the countdown counter which results in an undetermined countdown period for the ?rst period. the countdown value n will however be correctly stored and correctly loaded on subsequent timer periods. when the countdown timer ?ag is set, an interrupt signal on int will be generated provided that this mode is enabled. see section 8.7.2 for details on how the interrupt can be controlled. when starting the timer for the ?rst time, the ?rst period will have an uncertainty which is a result of the enable instruction being generated from the interface clock which is asynchronous with the timer source clock. subsequent timer periods will have no such delay. the amount of delay for the ?rst timer period will depend on the chosen source clock; see t ab le 29 . at the end of every countdown, the timer sets the countdown timer ?ag (bit tf). bit tf can only be cleared by software. the asserted bit tf can be used to generate an interrupt ( int). the interrupt can be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of bit tf. bit ti_tp is used to control this mode selection and the interrupt output can be disabled with bit tie. in the example it is assumed that the timer ?ag is cleared before the next countdown period expires and that the int is set to pulsed mode. fig 10. general countdown timer behavior table 29. first period delay for timer counter value n timer source clock minimum timer period maximum timer period 4096 hz n n + 1 64 hz n n + 1 1 hz (n - 1) + 1 64 hz n + 1 64 hz 1 60 hz (n - 1) + 1 64 hz n + 1 64 hz 001aaf906 n duration of first timer period after enable may range from n - 1 to n + 1 03 xx 02 01 03 02 01 03 02 01 03 n 03 xx countdown value, n timer source clock countdown counter te tf int
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 17 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar when reading the timer, the current countdown value is returned and not the initial value n. for accurate read back of the countdown value, the spi-bus clock (scl) must be operating at a frequency of at least twice the selected timer clock. since it is not possible to freeze the countdown timer counter during read back, it is recommended to read the register twice and check for consistent results. 8.6.3 timer ?ags when a minute or second interrupt occurs, bit msf is set to logic 1. similarly, at the end of a timer countdown, bit tf is set to logic 1. these bits maintain their value until overwritten by software. if both countdown timer and minute/second interrupts are required in the application, the source of the interrupt can be determined by reading these bits. to prevent one ?ag being overwritten while clearing another, a logic and is performed during a write access. the ?ag is reset by writing a logic 0 but its value is not affected by writing a logic 1. three examples are given for clearing the ?ags. flags msf and tf are cleared by a write command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. repeatedly re-writing these bits has no in?uence on the functional behavior. t ab le 31 , t ab le 32 and t ab le 33 show what instruction must be sent to clear the appropriate ?ag. clearing the alarm ?ag (bit af) operates in exactly the same way; see section 8.5.1 . 8.7 interrupt output an active low interrupt signal is available at pin int. operation is controlled via the bits of control register 2. interrupts can be sourced from three places: second/minute timer, countdown timer and alarm function. bit ti_tp con?gures the timer generated interrupts to be either a pulse or to follow the status of the interrupt ?ags (bits tf and msf). table 30. flag location in register control_2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 control_2 - - msf - af tf - - table 31. example to clear only tf (bit 2) in register control_2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 control_2 - - 1 - 1 0 - - table 32. example to clear only msf (bit 5) in register control_2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 control_2 - - 0 - 1 1 - - table 33. example to clear both tf and msf (bits 2 and 5) in register control_2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 control_2 - - 0 - 1 0 - -
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 18 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar remark: note that the interrupts from the three groups are wired-or, meaning they will mask one another; see figure 11 . 8.7.1 minute and second interrupts the pulse generator for the minute/second interrupt operates from an internal 64 hz clock and consequently generates a pulse of 1 64 second duration. if the msf ?ag is clear before the end of the int pulse, then the int pulse is shortened. this allows the source of a system interrupt to be cleared immediately it is serviced i.e. the system does not have to wait for the completion of the pulse before continuing; see figure 12 . instructions for clearing msf are given in section 8.6.3 . when bits si, mi, tie and aie are all disabled, pin int will remain high-impedance. fig 11. interrupt scheme 001aaf907 seconds counter si 0 1 msf: minute second flag clear set pulse generator 1 clear trigger te si mi minutes counter countdown counter mi from interface: clear msf to interface: read msf af: alarm flag clear set to interface: read af 0 1 tf: timer clear set pulse generator 2 clear trigger tie int from interface: clear tf from interface: clear af set alarm flag, af to interface: read tf ti_tp aie
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 19 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar the timing shown for clearing bit msf in figure 12 is also valid for the non-pulsed interrupt mode i.e. when bit ti_tp = 0, where the pulse can be shortened by setting both bits mi and si to logic 0. 8.7.2 countdown timer interrupts generation of interrupts from the countdown timer is controlled via bit tie; see t ab le 7 . the pulse generator for the countdown timer interrupt also uses an internal clock which is dependent on the selected source clock for the countdown timer and on the countdown value n. as a consequence, the width of the interrupt pulse varies; see t ab le 34 . [1] n = loaded countdown value. timer stopped when n = 0. if the tf ?ag is clear before the end of the int pulse, then the int pulse is shortened. this allows the source of a system interrupt to be cleared immediately it is serviced i.e. the system does not have to wait for the completion of the pulse before continuing; see figure 13 . instructions for clearing tf are given in section 8.6.3 . (1) indicates normal duration of int pulse (bit ti_tp = 1). fig 12. example of shortening the int pulse by clearing the msf ?ag 001aaf908 58 seconds counter msf int scl instruction 59 clear instruction 8th clock (1) table 34. int operation (bit ti_tp = 1) source clock (hz) int period (s) n = 1 [1] n > 1 4096 1 8192 1 4096 64 1 128 1 64 1 1 64 1 64 1 60 1 64 1 64
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 20 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar the timing shown for clearing bit tf in figure 13 is also valid for the non-pulsed interrupt mode i.e. when bit ti_tp = 0, where the pulse can be shortened by setting bit tie = 0. 8.7.3 alarm interrupts generation of interrupts from the alarm function is controlled via bit aie. if bit aie is enabled, the int pin follows the status of bit af. clearing bit af will immediately clear int. no pulse generation is possible for alarm interrupts; see figure 14 . (1) indicates normal duration of int pulse (bit ti_tp = 1). fig 13. example of shortening the int pulse by clearing the tf ?ag 001aaf909 01 countdown counter tf int scl instruction n clear instruction 8th clock (1) example where only the minute alarm is used and no other interrupts are enabled. fig 14. af timing 001aaf910 44 45 minute counter minute alarm af int scl instruction 45 clear instruction 8th clock
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 21 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar 8.8 clock output a programmable square wave is available at pin clkout. operation is controlled by control bits cof[2:0] in register clkout_control (0dh). frequencies of 32.768 khz (default) down to 1 hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. pin clkout is an open-drain output and enabled at power-on. when disabled the output is low. the duty cycle of the selected clock is not controlled, but due to the nature of the clock generation, all clock frequencies, except 32.768 khz, have a duty cycle of 50 : 50. the stop function can also affect the clkout signal, depending on the selected frequency. when stop is active, the clkout pin will generate a continuous low for those frequencies that can be stopped. for more details, see section 8.10 . [1] duty cycle de?nition: high-level time (%) : low-level time (%). 8.9 external clock test mode a test mode is available which allows for on-board testing. in this mode it is possible to set up test conditions and control the operation of the rtc. the test mode is entered by setting bit ext_test in register control_1 making pin clkout an input. the test mode replaces the internal signal with the signal applied to pin clkout. every 64 positive edges applied to pin clkout generates an increment of one second. the signal applied to pin clkout should have a minimum high width of 300 ns and a minimum period of 1000 ns. the internal clock, now sourced from pin clkout, is divided down to 1 hz by a 2 6 divide chain called a prescaler; see section 8.10 . the prescaler can be set into a known state by using bit stop. when bit stop is set, the prescaler is reset to 0. stop must be cleared before the prescaler can operate again. from a stop condition, the ?rst 1 second increment will take place after 32 positive edges on pin clkout. thereafter, every 64 positive edges will cause a 1 second increment. remark: entry into test mode is not synchronized to the internal 64 hz clock. when entering the test mode, no assumption as to the state of the prescaler can be made. operation example: table 35. clkout frequency selection bits cof[2:0] clkout frequency (hz) typical duty cycle [1] (%) effect of stop 000 32768 60 : 40 to 40 : 60 no effect 001 16384 50 : 50 no effect 010 8192 50 : 50 no effect 011 4096 50 : 50 clkout = low 100 2048 50 : 50 clkout = low 101 1024 50 : 50 clkout = low 110 1 50 : 50 clkout = low 111 clkout = low
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 22 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar 1. set ext_test test mode (register control_1, bit ext_test = 1). 2. set stop (register control_1, bit stop = 1). 3. clear stop (register control_1, bit stop = 0). 4. set time registers to desired value. 5. apply 32 clock pulses to pin clkout. 6. read time registers to see the ?rst change. 7. apply 64 clock pulses to pin clkout. 8. read time registers to see the second change. repeat steps 7 and 8 for additional increments. 8.10 stop bit function the stop bit function allows the accurate starting of the time circuits. the stop function will cause the upper part of the prescaler (f 2 to f 14 ) to be held at reset, thus no 1 hz ticks will be generated. the time circuits can then be set and will not increment until the stop is released; see figure 15 . stop will not affect the output of 32768 hz, 16384 hz or 8192 hz; see section 8.8 . the lower two stages of the prescaler (f 0 and f 1 ) are not reset and because the spi-bus is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between 0 and one 8192 hz cycle; see figure 16 . fig 15. stop bit functional diagram fig 16. stop bit release timing 001aaf911 osc 32768 hz 16384 hz osc stop detector f 0 f 1 f 13 res f 14 res f 2 res 2 hz 512 hz 16384 hz 8192 hz 1 hz tick stop clkout source reset 8192 hz 4096 hz 001aaf912 8192 hz stop released 0 m s to 122 m s
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 23 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar the ?rst increment of the time circuits is between 0.499888 s and 0.500000 s after stop is released. the uncertainty is caused by prescaler bits f0 and f1 not being reset; see t ab le 36 . [1] f 0 is clocked at 32.768 khz. table 36. example: ?rst increment of time circuits after stop release bit stop prescaler bits 1 hz tick time comment f 0 f 1 -f 2 to f 14 [1] hh:mm:ss clock is running normally 0 01-0 0001 1101 0100 12:45:12 prescaler counting normally stop is activated by user. f0f1 are not reset and values can not be predicted externally 1 xx-0 0000 0000 0000 12:45:12 prescaler is reset; time circuits are frozen new time is set by user 1 xx-0 0000 0000 0000 08:00:00 prescaler is reset; time circuits are frozen stop is released by user 0 xx-0 0000 0000 0000 08:00:00 prescaler is now running xx-1 0000 0000 0000 08:00:00 xx-0 1000 0000 0000 08:00:00 xx-1 1000 0000 0000 08:00:00 :: 11-1 1111 1111 1110 08:00:00 00-0 0000 0000 0001 08:00:01 0 to 1 transition of f14 increments the time circuits 10-0 0000 0000 0001 08:00:01 :: 11-1 1111 1111 1111 08:00:01 00-0 0000 0000 0000 08:00:01 10-0 0000 0000 0000 08:00:01 :: 11-1 1111 1111 1110 08:00:01 00-0 0000 0000 0001 08:00:02 0 to 1 transition of f14 increments the time circuits fig 17. increment of time circuit 001aaf913 0.499888 s to 0.500000 s 1 s
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 24 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar 8.11 3-line spi data transfer to and from the device is made via a 3-wire spi-bus; see t ab le 37 . the data lines for input and output are split. the data input and output lines can be connected together to facilitate a bidirectional data bus. the chip enable signal is used to identify the transmitted data. each data transfer is a byte, with the most signi?cant bit (msb) sent ?rst; see figure 18 . the transmission is controlled by the active high chip enable signal ce. the ?rst byte transmitted is the command byte. subsequent bytes will be either data to be written or data to be read. data is captured on the rising edge of the clock and transferred internally on the falling edge. the command byte de?nes the address of the ?rst register to be accessed and the read/write mode. the address counter will auto increment after every access and will reset to zero after the last valid register is accessed. the read/write bit (r/ w) de?nes if the following bytes will be read or write information. in figure 19 the seconds register is set to 45 seconds and the minutes register to 10 minutes. table 37. serial interface pin function description ce chip enable input when low, the interface is reset; pull-down resistor included; active input can be higher than v dd , but must not be wired high permanently scl serial clock input when pin ce = low, this input might ?oat; input can be higher than v dd sdi serial data input when pin ce = low, this input might ?oat; input can be higher than v dd ; input data is sampled on the rising edge of scl sdo serial data output push-pull output; drives from v ss to v dd ; output data is changed on the falling edge of scl fig 18. data transfer overview table 38. command byte de?nition bit symbol value description 7r/ w data read or data write selection 0 write data 1 read data 6 to 4 sa 001 subaddress; other codes will cause the device to ignore data transfer 3 to 0 ra 00h to 0fh register address range 001aaf914 command data bus chip enable data data data
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 25 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar in figure 20 the months and years registers are read. in this example, pins sdi and sdo are not connected together. in this con?guration, it is important that pin sdi is never left ?oating: it must always be driven either high or low. if pin sdi is left open, high i dd currents will result. fig 19. serial bus write example 001aaf915 xx address counter ce sdi scl 02 03 04 seconds data 45 bcd minutes data 10 bcd r/w addr 02 hex b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 1 b0 0 b7 0 b6 1 b5 0 b4 0 b3 0 b2 1 b1 0 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 0 fig 20. serial bus read example 001aaf916 xx address counter ce sdo sdi scl 07 08 09 months data 11 bcd years data 06 bcd r/w addr 07 hex b7 1 b6 0 b5 0 b4 1 b3 0 b2 1 b1 1 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 1 b1 1 b0 0
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 26 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar 9. internal circuitry 10. limiting values [1] hbm: human body model, according to jesd22-a114. [2] mm: machine model, according to jesd22-a115. [3] cdm: charged-device model, according to jesd22-c101. [4] latch-up testing, according to jesd78. fig 21. device diode protection diagram 001aaf895 osci osco int ce v ss v dd clkout scl sdi sdo PCA2125 table 39. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.5 +6.5 v i dd supply current - 50 +50 ma v i input voltage - 0.5 +6.5 v v o output voltage - 0.5 +6.5 v i i input current - 10 +10 ma i o output current - 10 +10 ma p tot total power dissipation - 300 mw t amb ambient temperature - 40 +125 c t stg storage temperature - 65 +150 c v esd electrostatic discharge voltage hbm [1] - 2000 v mm [2] - 200 v cdm [3] - 2000 v i lu latch-up current [4] - 100 ma
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 27 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar 11. static characteristics table 40. static characteristics v dd = 1.3 v to 5.5 v; v ss =0v; t amb = - 40 c to +125 c; f osc = 32.768 khz; quartz r s =60k w ; c l = 12.5 pf; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply: pin v dd v dd supply voltage spi-bus inactive; for clock data integrity [1] 1.3 - 5.5 v spi-bus active 1.6 - 5.5 v i dd supply current spi-bus active f scl = 6.0 mhz - - 500 m a f scl = 1.0 mhz - - 85 m a spi-bus inactive; clkout disabled; v dd = 2.0 v to 5.0 v [2] t amb =25 c - 550 - na t amb = - 40 c to +125 c - 760 1800 na spi-bus inactive (f scl = 0 hz); clkout enabled at 32 khz t amb =25 c v dd = 5.0 v - 1000 - na v dd = 3.0 v - 760 - na v dd = 2.0 v - 640 - na t amb = - 40 c to +125 c v dd = 5.0 v - - 2250 na v dd = 3.0 v - - 1950 na v dd = 2.0 v - - 1900 na inputs v i input voltage pin osci - 0.5 - v dd + 0.5 v v i input voltage pins ce, sdi, scl - 0.5 - 5.5 v v il low-level input voltage v ss - 0.3v dd v v ih high-level input voltage 0.7v dd -v dd v i l leakage current v i =v dd or v ss ; on pins sdi, scl and osci - 10 +1 m a c i input capacitance [3] --7pf r pd pull-down resistance pin ce - 240 550 k w outputs v o output voltage pins osco and sdo - - v dd + 0.5 v v o output voltage pins clkout and int; refers to external pull-up voltage - - 5.5 v v oh high-level output voltage pin sdo 0.8v dd -v dd v v ol low-level output voltage pin sdo v ss - 0.2v dd v v ol low-level output voltage pins clkout and int; v dd =5v; i ol = 1.5 ma v ss - 0.4 v
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 28 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar [1] for reliable oscillator start at power-up: v dd =v dd(min) + 0.3 v. [2] timer source clock = 1 60 hz; voltage on pins ce, sdi and scl at v dd or v ss . [3] implicit by design. 12. dynamic characteristics [1] bus will be held up by bus capacitance; use rc time constant with application values. i oh high-level output current pin sdo; v oh = 4.6 v; v dd = 5 v - - 1.5 ma i ol low-level output current pins int, sdo and clkout; v ol = 0.4 v; v dd =5v - 1.5 - - ma i ol low-level output current pin osco; v ol = 0.4 v; v dd =5v - 1--ma i lo output leakage current v o =v dd or v ss - 10 +1 m a c ext external capacitance - 25 - pf table 40. static characteristics continued v dd = 1.3 v to 5.5 v; v ss =0v; t amb = - 40 c to +125 c; f osc = 32.768 khz; quartz r s =60k w ; c l = 12.5 pf; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 41. dynamic characteristics v dd = 1.6 v to 5.5 v; v ss =0v; t amb = - 40 c to +125 c. all timing values are valid within the operating supply voltage at ambient temperature and referenced to v il and v ih with an input voltage swing of v ss to v dd . symbol parameter conditions v dd = 1.6 v v dd = 2.7 v v dd = 4.5 v v dd = 5.5 v unit min max min max min max min max pin scl f clk(scl) scl clock frequency - 1.5 - 4.76 - 5.00 - 6.25 mhz t scl scl time 660 - 210 - 200 - 160 - ns t clk(h) clock high time 320 - 100 - 100 - 70 - ns t clk(l) clock low time 320 - 110 - 100 - 90 - ns t r rise time - 100 - 100 - 100 - 100 ns t f fall time - 100 - 100 - 100 - 100 ns pin ce t su(ce) ce set-up time 30 - 30 - 30 - 30 - ns t h(ce) ce hold time 100 - 60 - 40 - 30 - ns t rec(ce) ce recovery time 100 - 100 - 100 - 100 - ns t w(ce) ce pulse width - 0.99 - 0.99 - 0.99 - 0.99 s pin sdi t su set-up time 25 - 15 - 15 - 10 - ns t h hold time 100 - 60 - 40 - 30 - ns pin sdo t d(r)sdo sdo read delay time bus load = 85 pf - 320 - 110 - 100 - 90 ns t dis(sdo) sdo disable time no load value [1] - 50 - 30 - 30 - 25 ns t t(sdi-sdo) transition time from sdi to sdo to avoid bus con?ict 0 - 0 - 0 - 0 - ns
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 29 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar fig 22. spi interface timing 001aag900 r/w sa2 ra0 b7 b6 b0 b7 b6 b0 b0 b6 b7 sdi sdo sdo hi z hi z sdi scl ce write read t w(ce) 80% 20% t clk(l) t f t h(ce) t rec(ce) t dis(sdo) t d(r)sdo t t(sdi-sdo) t r t h t su t clk(h) t su(ce)
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 30 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar 13. application information 13.1 application diagram 13.2 quartz frequency adjustment 1. method 1: ?xed osci capacitor a ?xed capacitor can be used whose value can be determined by evaluating the average capacitance necessary for the application layout; see figure 23 . the frequency is best measured via the 32.768 khz signal at pin clkout available after power-on. the frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average 5 10 - 6 ). an average deviation of 5 minutes per year can be easily achieved. 2. method 2: osci trimmer fast setting of a trimmer is possible using the 32.768 khz signal at pin clkout available after power-on. 3. method 3: osco output direct measurement of osco output (accounting for test probe capacitance). 14. test information 14.1 quality information this product has been quali?ed in accordance with the automotive electronics council (aec) standard q100 - stress test quali?cation for integrated circuits , and is suitable for use in automotive applications. the 1 farad capacitor is used as a standby and back-up supply. with the rtc in its minimum power con?guration i.e. timer off and clkout off, the rtc can operate for several weeks. fig 23. application diagram 001aaf918 osci 1 f supercapacitor osco int v ss v dd clkout ce scl sdi sdo PCA2125
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 31 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar 15. package outline fig 24. package outline sot402-1 (tssop14) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 32 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar 16. handling information inputs and outputs are protected against electrostatic discharge in normal handling. however, to be completely safe you must take normal precautions appropriate to handling mos devices; see jesd625-a and/or iec61340-5 . 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 17.3 wave soldering key characteristics in wave soldering are:
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 33 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities 17.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 25 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 42 and 43 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 25 . table 42. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 43. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 34 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 18. revision history msl: moisture sensitivity level fig 25. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 44. revision history document id release date data sheet status change notice supersedes PCA2125_1 20080728 product data sheet -
PCA2125_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 28 july 2008 35 of 36 nxp semiconductors PCA2125 spi real-time clock/calendar 19. legal information 20. data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 20.1 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 20.2 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 20.3 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 21. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors PCA2125 spi real-time clock/calendar ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 28 july 2008 document identifier: PCA2125_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 functional description . . . . . . . . . . . . . . . . . . . 3 8.1 register overview . . . . . . . . . . . . . . . . . . . . . . . 4 8.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.2.1 power-on reset override . . . . . . . . . . . . . . . . . . 6 8.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . 7 8.4 time and date function . . . . . . . . . . . . . . . . . . . 8 8.5 alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 10 8.5.1 alarm ?ag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.6 timer functions . . . . . . . . . . . . . . . . . . . . . . . . 13 8.6.1 second and minute interrupt. . . . . . . . . . . . . . 13 8.6.2 countdown timer function . . . . . . . . . . . . . . . . 15 8.6.3 timer ?ags . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.7 interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 17 8.7.1 minute and second interrupts . . . . . . . . . . . . . 18 8.7.2 countdown timer interrupts. . . . . . . . . . . . . . . 19 8.7.3 alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 20 8.8 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.9 external clock test mode. . . . . . . . . . . . . . . . . 21 8.10 stop bit function . . . . . . . . . . . . . . . . . . . . . . 22 8.11 3-line spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 26 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 11 static characteristics. . . . . . . . . . . . . . . . . . . . 27 12 dynamic characteristics . . . . . . . . . . . . . . . . . 28 13 application information. . . . . . . . . . . . . . . . . . 30 13.1 application diagram . . . . . . . . . . . . . . . . . . . . 30 13.2 quartz frequency adjustment . . . . . . . . . . . . . 30 14 test information . . . . . . . . . . . . . . . . . . . . . . . . 30 14.1 quality information . . . . . . . . . . . . . . . . . . . . . 30 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 31 16 handling information. . . . . . . . . . . . . . . . . . . . 32 17 soldering of smd packages . . . . . . . . . . . . . . 32 17.1 introduction to soldering . . . . . . . . . . . . . . . . . 32 17.2 wave and re?ow soldering . . . . . . . . . . . . . . . 32 17.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 32 17.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 33 18 revision history . . . . . . . . . . . . . . . . . . . . . . . 34 19 legal information . . . . . . . . . . . . . . . . . . . . . . 35 20 data sheet status . . . . . . . . . . . . . . . . . . . . . . 35 20.1 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 20.2 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 35 20.3 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35 21 contact information . . . . . . . . . . . . . . . . . . . . 35 22 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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